Ocin tsim - DVFS Aware Simulator for NoCs

Networks-on-Chip (NoCs) are a general purpose, scalable replacements for shared medium wired interconnects offering many practical applications in industry. Dynamic Voltage Frequency Scaling (DVFS) is a technique whereby a chip’s voltage-frequency levels are varied at run time, often used to conserve dynamic power. Various DVFS-based optimization techniques have been proposed; however, few have been implemented, in part due to the resources required to validate architectural decisions through prototyping. As a result, designers are faced with a lack of insight into potential power savings or performance gains at early architecture stages. This paper proposes a DVFS aware NoC simulator with support for per node power-frequency modeling to allow the fine-tuning of such optimization techniques early on in the design cycle. The proposed simulator also provides a framework for benchmarking various candidate strategies to allow selective prototyping.